A Low Jitter PLL Using High PSRR Low-Dropout Regulator

of the Thesis A Low Jitter PLL Using High PSRR Low-Dropout Regulator by Gyunam Jeon Master of Science in Electrical and Computer Engineering Northeastern University, June 2015 Dr. Yong-Bin Kim, Adviser In the recent years, the world has seen a huge boom in portable electronic products like cell phones, tablets, etc. Most of the products are powered by a battery that requires a power supply noise management circuitry to optimize the performance. As a result, lots of recent researches have been proposed across the world in battery’s power supply noise management field to improve power consumption and also to reduce the cost of integrated chips. Phase-Locked Loop (PLL) is a feedback system that forces a voltage controlled oscillator to replicate and track the frequency and phase at the input when in lock[1, 2]. It is a control system allowing one oscillator to track with another. The PLL is widely used and its usage is continuously increasing in modern integrated circuit design such as synthesizers and clock generators [3].